DESIGNING A HIGH SPEED LOW POWER OF TWO STAGE DYNAMIC COMPARATOR
PG Scholar , Department of Electronics and Communication Engineering, Velalar College of Engineering and Technology, Erode, India
ABSTRACT
Designing a high speed, low power of two stage dynamic comparator is presented.Low power consumption is a great interest because it increases the battery lifetime.The main block in many applications is the analogue to digital converter (ADC) which serves as an interface between the analog world and a digital processing unit. In this circuit the first stage of the preamplifier stage is limited to vdd/2 and NMOS is connected at the second stage for reducing power consumption. The second stage of the comparator is to start comparison based on inputs and reference voltages. Simulation results prove that the proposed comparator speed ups the conventional comparator and also reduces power. Furthermore, proposed comparator is followed by post layout. This method will be designed and its power is evaluated in the ASIC design GUI software of 130 nm technology.
