Design and Implementation of 8x8 VEDIC Multiplier Using GDI Logic
K.M.Pattani
, B.H.Nagpara, Ravi S.Patel
Asst. Professor C. U. Shah College of Engineering and Technology Department of E&C, Wadhwan, Gujarat, India, India
Asst. Professor C. U. Shah College of Engineering and Technology Department of E&C, Wadhwan, Gujarat, India, India
Vol. 3, Issue 3 pp. 35-41 🌐 Open Access
ABSTRACT
Multiplication is one of the basic operations for any high speed digital logic system design, digital signal processors or communication system. Primary issues in design of multiplier are area, delay, and power dissipation. There are many algorithms like booth multiplier, array multiplier, vedic multiplier, compressor based vedic multiplier for overcoming this problems. This paper mainly presents VEDIC multiplier using Urdhva Tiryagbhyam Sutra and it uses Full Adder, Ripple Carry Adder, and basic gates. GDI allows reduce power consumption, delay and area of any digital circuits while maintain low complexity of logic design. The design has been implemented using 45nm GDI technology at 1.0v supply voltage in LTSpice IV tool.
Keywords:
Vedic Multiplier, Urdhva Tiryagbhyam Sutra, Gate Diffusion Input, GDI 45nm Technology, Ripple Carry Adder, Simulation Results, Comparison
