Design And Performance Analysis Of 8x8 Vedic Multiplier Using Submicron Technology

Authors

  • B.H.Nagpara Asst. Professor C. U. Shah College of Engineering and Technology,Department of E&C, Wadhwan, Gujarat, India
  • K.M.Pattani Asst. Professor C. U. Shah College of Engineering and Technology,Department of E&C, Wadhwan, Gujarat, India
  • Ravi S.Patel P.G.Student C. U. Shah College of Engineering and Technology,Department of E&C, Wadhwan, Gujarat, India

Keywords:

Vedic Multiplier, Urdhva Tiryagbhyam Sutra, CMOS 45nm Technology, Gate Diffusion Input, GDI 45nm Technology, Ripple Carry Adder, Simulation Results, Comparison

Abstract

Multiplication is one of the basic operations for any high speed digital logic system design, digital signal
processors or communication system. Primary issues in design of multiplier are area, delay, and power dissipation. There are
many algorithms like booth multiplier, array multiplier, vedic multiplier, compressor based vedic multiplier for overcoming
this problems. This paper mainly presents VEDIC multiplier using Urdhva Tiryagbhyam Sutra and it uses Full Adder, Ripple
Carry Adder, and basic gates. The design has been implemented using 45nm CMOS and GDI technology at 1.0v supply
voltage in LTSpice IV tool.

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Published

2016-04-25

How to Cite

B.H.Nagpara, K.M.Pattani, & Ravi S.Patel. (2016). Design And Performance Analysis Of 8x8 Vedic Multiplier Using Submicron Technology. International Journal of Advance Research in Engineering, Science & Technology, 3(4), 382–387. Retrieved from https://ijarest.org/index.php/ijarest/article/view/560

Issue

Vol. 3 No. 4 (2016): Volume: 03, Issue: 04 - April, 2016.

Section

Articles