Design and Implementation of 8x8 VEDIC Multiplier Using GDI Logic

Authors

  • K.M.Pattani Asst. Professor C. U. Shah College of Engineering and Technology Department of E&C, Wadhwan, Gujarat, India
  • B.H.Nagpara Asst. Professor C. U. Shah College of Engineering and Technology Department of E&C, Wadhwan, Gujarat, India
  • Ravi S.Patel P.G.Student C. U. Shah College of Engineering and Technology,Department of E&C, Wadhwan, Gujarat, India

Keywords:

Vedic Multiplier, Urdhva Tiryagbhyam Sutra, Gate Diffusion Input, GDI 45nm Technology, Ripple Carry Adder, Simulation Results, Comparison

Abstract

Multiplication is one of the basic operations for any high speed digital logic system design, digital signal
processors or communication system. Primary issues in design of multiplier are area, delay, and power dissipation.
There are many algorithms like booth multiplier, array multiplier, vedic multiplier, compressor based vedic multiplier
for overcoming this problems. This paper mainly presents VEDIC multiplier using Urdhva Tiryagbhyam Sutra and it
uses Full Adder, Ripple Carry Adder, and basic gates. GDI allows reduce power consumption, delay and area of any
digital circuits while maintain low complexity of logic design. The design has been implemented using 45nm GDI
technology at 1.0v supply voltage in LTSpice IV tool.

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Published

2016-03-25

How to Cite

K.M.Pattani, B.H.Nagpara, & Ravi S.Patel. (2016). Design and Implementation of 8x8 VEDIC Multiplier Using GDI Logic. International Journal of Advance Research in Engineering, Science & Technology, 3(3), 35–41. Retrieved from https://ijarest.org/index.php/ijarest/article/view/455

Issue

Vol. 3 No. 3 (2016): Volume: 03, Issue: 03 - March, 2016.

Section

Articles