A 16-bit Booth Multiplier Design Using GDI Logic Style

Authors

  • Lakum kalpesh Student M.tech EC in C U Shah Engineering Collage, Kothariya, Surendranagar
  • B.H.Nagpara Assistant professor at C U Shah Engineering Collage, Kothariya, Surendranagar

Keywords:

Booth Multiplier, GDI logic, CMOS technique, 45nm technology, TANNER EDA simulation result

Abstract

Gate Diffusion input (GDI) is a newest technology of designing a low power digital combinational circuit is described. This
method allows reduce power consumption, Delay and area of any digital circuits while maintain low complexity of logic design. The
GDI allow implementing of a wide range of complex logic function using only two transistors. This technique is prefer for designing
fast using less number of transistors while improving logic level for swing and static power characteristics and also allows simple
design by using smaller cell library. Comparision of GDI transistor count with CMOS and also Compare Power consumption and
delay. Simulation result shows that the propose GDI has been good performance in compared to CMOS design
In this paper, the 16-bit Booth multiplier is design based on GDI and the simulations are performed by TANNER TOOL
based on 45nm GDI logic.

Published

2015-05-25

How to Cite

Lakum kalpesh, & B.H.Nagpara. (2015). A 16-bit Booth Multiplier Design Using GDI Logic Style. International Journal of Advance Research in Engineering, Science & Technology, 2(5), 99–102. Retrieved from https://ijarest.org/index.php/ijarest/article/view/128