2.4 Gbps CLOCK AND DATA RECOVERY USING CMOS 45nm TECHNOLOGY

Authors

  • Hiren B. Ravisaheb P.G. Student, Dept. of EC, C. U. Shah College of Engineering & Technology, Wadhwancity ,Gujarat
  • Bharat H. Nagpara Asst. Prof. , Dept. of EC, C. U. Shah College of Engineering & Technology, Wadhwancity, Gujarat

Keywords:

Phase Frequency Detector, Charge Pump, Low Pass Filter, Voltage Controlled Oscillator, Retimed Data Circuit, LT Spice Tool.

Abstract

The bandwidth demands of modern computing systems have been continually increasing and the recent
focus on parallel processing will only increase the demands placed on data communication circuits. As data rates
enter the 2.4Gb/s range, serial data communication architectures become attractive as compared to parallel
architectures. Serial architectures have long been used in fiber optic systems for long-haul applications, The
integration of clock and data recovery circuits into monolithic integrated circuits is attractive as it improves
performance and reduces the system cost, The functionality and implementation of these circuits will be checked in
LTspice using standard 45nm CMOS technology.

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Published

2017-03-25

How to Cite

Hiren B. Ravisaheb, & Bharat H. Nagpara. (2017). 2.4 Gbps CLOCK AND DATA RECOVERY USING CMOS 45nm TECHNOLOGY. International Journal of Advance Research in Engineering, Science & Technology, 4(3), 383–389. Retrieved from https://ijarest.org/index.php/ijarest/article/view/950

Issue

Vol. 4 No. 3 (2017): Volume: 04, Issue: 03 - March, 2017.

Section

Articles