Design & Simulation of Dual Elevator Controller using FPGA

Authors

  • Miss Harshita Soni Electronics & Communication Engineering, M.B.I.C.T College, New V.V. Nagar, Gujarat, India
  • Mr. Ashish Purani Technical Associate, e-info chips Training & research Academy, Ahmedabad, Gujarat, India
  • Mr. Vipul Dabhi Assistant Professor, M.B.I.C.T College New V.V.Nagar, Gujarat, India

Keywords:

Verilog HDL, Xilinx 14.2 tool

Abstract

This paper presents for Dual Elevator Controller. Dual Elevator controller “moves people or goods up & down in the buildings
or mines, which controls two elevators”. Elevator Controller controls the entire operation of the Dual Elevator system. The
elevator controller also reads the status, if any, from any of the request positions through the flip-flops. If the door of any elevator
is open, the timer signals from the elevator keep controller informed of being busy. The control state machine receives all these
signals. It is programmed by the algorithm by which it should control the system. In this work, the real time Elevator units &
Controller units are modeled with verilog HDL code using Finite State Machine (FSM) model to achieve the logic in optimized
way.

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Published

2015-04-25

How to Cite

Miss Harshita Soni, Mr. Ashish Purani, & Mr. Vipul Dabhi. (2015). Design & Simulation of Dual Elevator Controller using FPGA. International Journal of Advance Research in Engineering, Science & Technology, 2(4), 189–191. Retrieved from https://ijarest.org/index.php/ijarest/article/view/71

Issue

Vol. 2 No. 4 (2015): Volume: 02, Issue: 04 - April, 2015.

Section

Articles