Design of 16-bit Architecture for KLE Processor

Authors

  • Kanchan Joshi M.Tech VLSI, Dept. of ECE, KLE Dr. MSSCET Belagavi, India
  • Shruthi M.Tech VLSI, Dept. of ECE, KLE Dr. MSSCET Belagavi, India
  • Mohasinali Attar M.Tech VLSI, Dept. of ECE, KLE Dr. MSSCET Belagavi, India
  • Rahul Patil M.Tech VLSI, Dept. of ECE, KLE Dr. MSSCET Belagavi, India
  • Dr.U.V.Wali Professor, Dept. of ECE, KLE Dr. MSSCET Belagavi, India

Keywords:

6T SRAM, , RISC, Program Counter, ISA, PLL, Cadence Tool, Xilinx

Abstract

Design of a Microprocessor is a combination of many combinational and sequential circuits. The present paper describes the
modules such as datapath, ISA, clock system and memory unit’s design and implementation for the microprocessor design work
being taken up at the college level. The need of today’s VLSI technology is to implement all the modules with less power
consumption and high speed operation. The proposed architecture is the design and implementation of 16-bit Processor using
Verilog HDL and Cadence tools for the design of Processor undertaken by the students. At KLE Dr. MSSCET College, a project
has been envisioned to develop a microprocessor from the architectural to physical level implementation. A RISC based VonNeumann architecture design of KLE microprocessor is developed.

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Published

2015-06-25

How to Cite

Kanchan Joshi, Shruthi, Mohasinali Attar, Rahul Patil, & Dr.U.V.Wali. (2015). Design of 16-bit Architecture for KLE Processor. International Journal of Advance Research in Engineering, Science & Technology, 2(6), 25–28. Retrieved from https://ijarest.org/index.php/ijarest/article/view/207

Issue

Vol. 2 No. 6 (2015): Volume: 02, Issue: 06 - June, 2015

Section

Articles