Implementation Of 32-Bit Kogge-Stone Adder Using FPGA Technology

Authors

  • Ms. Aishwarya Hiremath Department of ECE,SDM College of Engineering, Dharwad
  • Prof. Bairu K.Saptalakar Department of ECE,SDM College of Engineering, Dharwad

Keywords:

Kogge-Stone adder, FPGA, Power, Verilog, Xilinx 14.5

Abstract

The binary adder is the basic component in most computerized circuit outlines including advanced sign
processors(DSP) and in data paths of microprocessor units. The extensive research continues to be focused on improving
the power delay performance of the adder. In VLSI usage, Parallel prefix adders are known to have the best
performance. Among the parallel prefix adders Kogge-Stone adder (KSA) has reduced power consumption and high
speed. This paper explores the 32-bit KSA with modification in its architecture. The analysis of original KSA architecture
and the modified KSA is compared and results are calculated. This project is carried out using the SPARTAN-3 and the
software tool XILINX version 14.5. Simulation is carried out using ISIM.

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Published

2016-05-25

How to Cite

Ms. Aishwarya Hiremath, & Prof. Bairu K.Saptalakar. (2016). Implementation Of 32-Bit Kogge-Stone Adder Using FPGA Technology. International Journal of Advance Research in Engineering, Science & Technology, 3(5), 580–587. Retrieved from https://ijarest.org/index.php/ijarest/article/view/672

Issue

Vol. 3 No. 5 (2016): Volume: 03, Issue: 05 - May, 2016.

Section

Articles