IMPLEMENTATION AND COMPARITIVE STUDY OF VEDIC MULTIPLIERS WITH DIFFERENT ADDERS USING URDHVA-TIRYAKBHYAM SUTRA

Abstract

Multiplier is the vital component and key block in high speed processor or computing machine like ALU,MAC,DSP,FFTs,etc.
With the increasing constrains on delay, more emphasis is being laid on design of faster multiplications. To enhance speed many
modifications over the standard modified booth algorithm, Wallace tree methods for multiplier design have been made.Amongest
these Vedic multipliers based on Vedic mathematics are presently under focus due to these being one of the fastest and low power
multiplier. There are sixteen sutras in Vedic multiplication in which Urdhva- Tiryakbhyam has been noticed to be the most
efficient one in terms of speed. I n this paper design and implementation of 64x64 Vedic multiplier is described. It has been
modified with different adders and performance is compared in terms of propagation delay. It is proved that Vedic multiplier with
simple adder achieves minimum propagation delay.