Vedic Multiplier Using Efficient Compressor to Reduce the Delay for Vedic Multiplier and Pipelining

Abstract

With the new technology and new innovation in the VLSI, it is used for the high speed communication
and the signal processing. Vedic mathematics gives the fast operation and it reduces the delay and almost power
constant. So we can perform the fast operation and can calculate fastly with the help of Vedic mathematics. The
structure uses 15:2 compressor using 3:2 and 7:2 compressor architecture. In addition it uses “Urdhwa Tiryakbhyam
Sutra” of Vedic mathematics and reducing the delay using pipelining technique. This all procedure is carried out in
Xilinx ISE Design Suite 13.2_1 software and gives us the delay and power get improve. More often than not,
performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications
performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic
multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled
combination for serving any complex multiplication computations. Vedic multiplier known as “Urdhva
Tiryakbhayam” meaning vertical and crosswise implemented using reversible logic, which is the first of its kind. This
multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging,
software defined radios, wireless communications.