Effect of Variability on Performance of CNFET Based Digital Circuits

Abstract

Nowadays, Electronics trend is continuously reducing feature sizes, and employing continuously smaller
components on integrated circuits, new challenges arise on the way of silicon CMOS circuits and devices. Emerging
“Nano-devices” promise the possibility of increased integration density and reduced power consumption. The Carbon
Nano-Tube (CNT) is one such device which is also the device of choice in this work. This work is concerned with building
reliable systems out of these unreliable components. The work was done in HSPICE with the help of the Stanford CNFET
model. By use of CNFET in logic gates, delay and power reduced by 4.14% and 28.19% respectively as compared to
CMOS. By applying this technique on digital circuits we will improve the above results.