Design of Low Power DRAM in 90nm Technology
Keywords:
Cell, Power Dissipation, Scalable, CMOS, leakage current, etc.Abstract
The semiconductor industry is trying to catch up with Moore’s law by scaling the devices namely microprocessor and
memories. Reduction in size guarantees reduction of its parasitic mainly capacitance. The parasitic mainly contribute to increment
of size and unnecessary power dissipation in the overall device as a well designed layout of chip ensures quality of work and better
performance. Memories are circuits or systems that store digital information in large quantity. This paper is on the analysis and
design of CMOS.Memories namely DRAM and associated peripheral circuits. Semiconductor memory is classified on the basis of
functionality, access patterns and nature of storage mechanism. Then, we shall move into some proposed models, which have more
functional advantages with respect to data retention stability, power consumption, leakage power etc. Briefing of the functioning of
the circuits along with issues and benefits will be done in the following matter. To implement circuits, software named Digital
Schematic (DSCH) editor will be effectively used. This software has the ability to automatically generate Verilog code. MicroWind
is another software which we will need to perform power analysis, which uses automation to form layouts of the circuits and
subsequently, determining the layout area and power dissipation
