Development of Verification IP for DDR2 memory with performance monitor

Authors

  • Gorwadia Sumit PG student [VLSI system design], Elect. & Comm. department., MEFGI, Rajkot, Gujarat
  • Mr. Jayesh Popat Assist. Prof., Elect. & Comm. department., MEFGI, Rajkot, Gujarat

Keywords:

UVM, Verification, Environment, Verification IP, memory verification, System Verilog

Abstract

The goal of function verification is to find the errors in the design given by the engineers and to check the
functionality of that design whether it give the expected output if not then change the design according to it to get desired
functionality of DUT (design under test). This paper show the latest approach to meet above requirement using the UVM
(Universal Verification Methodology).

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Published

2017-05-25

How to Cite

Gorwadia Sumit, & Mr. Jayesh Popat. (2017). Development of Verification IP for DDR2 memory with performance monitor. International Journal of Advance Research in Engineering, Science & Technology, 4(5), 80–85. Retrieved from https://ijarest.org/index.php/ijarest/article/view/1503

Issue

Vol. 4 No. 5 (2017): Volume: 04, Issue: 05 - May, 2017.

Section

Articles