PERFORMANCE ENHANCEMENT OF CARRY SPECULATIVE ADDER FOR LOW POWER VLSI

Abstract

Addition is one of the most commonly used arithmetic operation, which adds two operands and
used to build advanced operations such as multiplication and division. They are generally used in
applications such as arithmetic logic units and digital signal processors. The existing adders suffer from
area overhead, critical path delay and power consumption. Low power is essential for portable
multimedia devices employing various signal processing algorithms and architectures. Speculative adders
are designed with variable latency that combines speculation technique in addition with correction
methodology to attain high performance in terms of low area overhead. Carry Speculative Adder(CSPA)
uses carry predictor circuit in order to reduce power consumption and computational time. It also uses
error detection and error recovery circuit to detect the fault occured in the partial sum generator and to
recover it to get accurate results. CSPA circuit produces error free output so that it can be used in many
applications. This speculative adder can reduce the delay upto 11.89%.