DESIGN AND ANALYSIS OF VEDIC MULTIPLIER BASED ON YAVADUNAM TAVADUNIKRITYA VARGA YOJAYET SUTRA
Keywords:
Vedic mathematics, “Yavadunam Tavadunikritya Varga Yojayet”, Wallace tree multiplier, BaughWooley multiplierAbstract
In the modern world of digitization, processing of data in real time requires an increase in the
operating speed of a system. The use of Vedic mathematics lies in the formula that reduces the typical
calculation in the conventional mathematics to very simple one. This paper deals with the design of Vedic
multiplier using “Yavadunam Tavadunikritya Varga Yojayet” of ancient Indian Vedic mathematics. The
Unique architecture is designed for “Yavadunam Tavadunikritya Varga Yojayet” sutra. Which uses the
multipliers and a comparison of the power, delay and area constraints are obtained using Xilinx Spartans 3E
which using the Wallace tree multiplier in the proposed method power and delay are significantly low
compared to the other multipliers such as array and Baugh-Wooley multiplier.