Comparative Study on Pipelined and Parallel Multiplier using Vedic Mathematics: A Review
Keywords:
Vedic mathematics, ALU, multiply and Accumulated (MAC), igital Signal processing, graphics processing units (GPUs), System-on-Chip (SoC).Abstract
Vedic mathematics is the name given to the ancient Indian system of mathematics that was
rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). The design of high speed
Vedic multiplier using the techniques of Vedic Mathematics that have been modified to improve performance
A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most
digital signal processing systems as well as in general processors. A typical processor devotes a considerable
amount of processing time in performing arithmetic operations, particularly multiplication operations.
Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources
and processing time than addition and subtraction. Multiplication is a critical operation of Digital Signal
processing (DSP) applications, Arithmetic and Logic Unit (ALU), multiply and Accumulated (MAC) unit.
High Speed Multiplication is thus an essential requirement to increase the performance of processor. This
paper reviews the design of a low power high speed algorithms for arithmetic logic units using this ancient
mathematics techniques. The synthesized design using Xilinx ISE tool and Spartan3E.
