DESIGN AND IMPLEMENTATION OF ERROR CONTROL CODE USING LOW POWER VLSI TECHNIQUE
Keywords:
Low Density Parity Check (LDPC) codes, iterative decoding, Sum Product algorithm, Low Power, FEC(Forward Error Correction), Check Node Unit(CNU), Variable Node Unit(VNU)Abstract
In this paper for Error control code Low Density Parity Check (LDPC) Codes are chosen as it offer
remarkable error correction performance and therefore increase the design space for communication systems. This
performance made them suitable for many modern applications such as Digital Satellite Broadcasting system (DVBS2), Wireless Local Area Network (IEEE 802. 1 1n) and Metropolitan Area Network (802.16e). The decoding process
of these codes is based on an iterative algorithm that requires many computational cycles. This paper mainly presents
the modified normal sum product algorithm which gives accurate result compared to other existing systems. Clock
gating technique is mainly used in the proposed paper to reduce the dynamic power consumption. The proposed
LDPC Decoder architecture is simulated on Xilinx 14.5 ISE Simulator and implemented on Spartan 6 using Verilog
code.
