DESIGN AND IMPLEMENTATION OF HIGH SPEED 128-BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER

Authors

  • MURALIDHARAN.R ELECTRONICS AND COMMUNICATION ENGINEERING, SRM UNIVERSITY , CHENNAI
  • GIRIDHAR GOURAV.P ELECTRONICS AND COMMUNICATION ENGINEERING, SRM UNIVERSITY, CHENNAI
  • RAVURI VISHWANTH SAI ELECTRONICS AND COMMUNICATION ENGINEERING, SRM UNIVERSITY , CHENNAI
  • VINEEL KUMAR REDDY ELECTRONICS AND COMMUNICATION ENGINEERING, SRM UNIVERSITY , CHENNAI

Keywords:

Binary to Excess-1 Converter (BEC), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Modified Square root CSLA (Modified SQRT CSLA)

Abstract

Adders are the most widely used digital component. Carry Select Adder (CSLA) is one of the fast adders which is
used for the fast arithmetic operations. The carry-select adder is simple but rather fast, having a gate level depth of
O(√n). The area and the power consumption of the Ripple carry adders of CSLA are more. By modifying structure
of CSLA in gate level, the power and the area of the adder is reduced. The square root CSLA is modified with BEC
for reduction of area and power consumption. The modified square root CSLA is designed for 8-bit, 16-bit, 32-bit,
64 bit and 128-bit. The performance of modified square root CSLA improved than the regular CSLA. The proposed
design is implemented in Xilinx ISE.

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Published

2015-10-25

How to Cite

MURALIDHARAN.R, GIRIDHAR GOURAV.P, RAVURI VISHWANTH SAI, & VINEEL KUMAR REDDY. (2015). DESIGN AND IMPLEMENTATION OF HIGH SPEED 128-BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER. International Journal of Advance Research in Engineering, Science & Technology, 2(10), 100–104. Retrieved from https://ijarest.org/index.php/ijarest/article/view/320

Issue

Vol. 2 No. 10 (2015): Volume: 02, Issue: 10 - October, 2015.

Section

Articles