SCALING CHALLENGES IN CMOS TECHNOLOGY

Abstract

This paper explores scaling challenges in CMOS transistor. Conventional devices have been scaled by thinning gate dielectrics,
forming shallower extensions, increasing channel doping, and lowering power supply voltages. Many of these key scaling
methods are reaching fundamental limitations. New thin body device architectures such as FinFETs are emerging which do not
rely on the conventional scaling approach. The short channel effects for these new device options improve as the channel
thickness is reduced. A brief overview of transistor architectures such as extremely thin silicon-on-insulator and MUGFET
(FinFET), as well as nanowire device architectures are discussed here.