SURVEY OF MEMORY HIERARCHY AND HYBRID MEMORY CUBE

Authors

  • Prof. Arun Tigadi Department of Electronics and Communication Engineering, KLE’s Dr. M S Sheshgiri College of Engineering and Technology Belagavi, Karnataka
  • Rahul C Kodaganur Department of Electronics and Communication Engineering, KLE’s Dr. M S Sheshgiri College of Engineering and Technology Belagavi, Karnataka
  • Prof Pramod Naik Department of Electronics & Communication Engineering, VCET, Puttur, Karnataka, India
  • Dr. Hansraj Guhilot Principal K.C.College of Engineering & Management Studies and Research ,Thane, Maharashtra,India

Keywords:

memory hierarchy, hybrid memory cube, primary memory, cache memory, registers

Abstract

All computers have a memory hierarchy; it is the classification of storage elements based on their capacity, cost and access
times. Most modern CPUs are so fast that for most program workloads, the bottleneck is the locality of reference of memory accesses
and the efficiency of the caching and memory transfer between different levels of the hierarchy. As a result, the CPU spends much of
its time idling, waiting for memory I/O to complete. The main goal of memory hierarchy is to provide CPU with necessary data (and
instructions) as quickly as possible. In this paper we review different types of memories in the memory hierarchy and evolution of
DRAM. We also investigate the recent trends in primary memory such as 'Hybrid Memory Cube', which is a three-dimensional DRAM
architecture that improves latency, bandwidth, power and density.

Published

2015-05-25

How to Cite

Prof. Arun Tigadi, Rahul C Kodaganur, Prof Pramod Naik, & Dr. Hansraj Guhilot. (2015). SURVEY OF MEMORY HIERARCHY AND HYBRID MEMORY CUBE. International Journal of Advance Research in Engineering, Science & Technology, 2(5), 338–343. Retrieved from https://ijarest.org/index.php/ijarest/article/view/177