Design Approach for FPGA Implementation of 16-Bit Vedic Multiplier

Abstract

In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and
high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the
intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional
adder structures. A Novel technique for digit multiplication namely Vedic multiplication has been introduced which is
quite different from normal multiplication by shift and addition operations. Normally a multiplier is a key block in
almost all the processors and also introduces high delay block and also a major power dissipation source. This paper
presents a new design methodology for less delay and less power efficient Vedic Multiplier based up on ancient Vedic
Mathematic techniques. This paper presents a technique for N×N multiplication is implemented and gives very less
delay for calculating multiplication results for 16×16 Vedic multiplier. In this paper, the main goal is to design the
high speed and low power and area efficient Vedic multiplier based on the crosswise and vertical algorithm.
Comparisons with existing conventional fast adder architectures have been made to prove its efficiency. The
performance analysis shows that the proposed architecture achieves three fold advantages in terms of delay-areapower. The synthesis results of the Vedic multiplier has compared with the booth, array multiplier by different
technologies. Booth multipliers are generally used for multiplication purposes. Booth Encoder, Wallace Tree, Binary
Adders and Partial Product Generator are the main components used for Booth multiplier architecture. Booth
multiplier is mainly used for 2 applications are to increase the speed by reduction of the partial products and also by
the way that the partial products to be added. The Vedic mathematics mainly reduces the complex typical calculations
in to simpler by applying sutras as stated above. These Vedic mathematic techniques are very efficient and take very
less hardware to implement. These sutras are mainly used for multiplication of two decimal numbers and we extend
these sutras for binary multiplications. Multiplexer is also called Universal element or Data Selector. A Multiplexer
has of 2^n inputs have n select lines Basically MUX operation based on the select lines. Depending upon the select
line the input is Send to the output. Multiplexers used to increase the amount of data that can be sent over the
network. The values of 4 bit can be taken and remaining can be obtained from the next blocks. Like that we will
obtain totally sixteen outputs and those are outputs of the sixteen bit addition.