VLSI ARCHITECTURE FOR HIGH THROUGHPUT COMPUTATION OF MULTILEVEL HAAR WAVELET TRANSFORM

Abstract

This paper presents a high precision low area lifting based architecture for the unified
implementation of both lossy and lossless 3D multi-level Discrete Wavelet Transform (DWT) using Haar
Transformer. The proposed system is parallel-pipelined, and resource is shared between the lossy and
lossless modes, producing a throughput of 2 outputs/clock and achieving a high speed and low area
solution. The data width of the design is taken as 20 bits to reach a high PSNR value for multi-level 3D
DWT. Targeting a portable and real-time solution, the proposed architecture was successfully
implemented on Xilinx Virtex-5 series Field Programmable Gate Array (FPGA), achieving a clock speed
of 290 MHz with a power consumption of 467 mW at 200 MHz clock frequency. The design has also been
implemented in UMC 90 nm CMOS technology, which consumes 329 mW power at 200 MHz clock
frequency. The proposed solution may be configured as lossless compression, in the field of 3D image
compression system, according to the necessity of the user.